A double-data rate (“DDR”) system includes a transmit circuit for transmitting serial data, having a particular duty-cycle, to a receiving circuit. Most receive circuits include a clock circuit for synchronizing the incoming serial data. In particular, the sampling clocks are recovered by looking at the incoming data stream and aligning sampling edges to the center of the data eyes or data cells. Ideally, the incoming serial data has a 50% duty-cycle.
However, a receive circuit may receive incoming data that has duty-cycle distortion and does not have the ideal 50% duty-cycle. First, a transmit clock circuit may generate a clock signal used for transmitting the data that does not have the ideal 50% duty-cycle. The transmit clock circuit may include Complementary Metal Oxide Semiconductor (“CMOS”) transistors that may be prone to random variations that introduce errors in the transmit clock signal. Second, a receive circuit introduces errors. For example, the receive circuit observes or reacts to rising edges faster than falling edges of a received data signal. Once again, this may cause a receiver recovered clock that is not centered at a data eye. Third, channel effects may cause duty-cycle distortion. For example, the medium used in transferring the serial data between the transmit circuit and receive circuit introduces delays that skew the expected data eye. Fourth, the receive clock itself may have a duty-cycle distortion present in it which may cause the input data to appear distorted when sampled by the receive clock.
Therefore, it is desirable to provide a circuit, apparatus and method for reducing the errors in obtaining data values caused by duty-cycle distortion.